Electronics devices, such as computer systems, music players, or cellular phones, rely on metal-oxide-semiconductor (MOS) for their key functions and features. Demands for more features and smaller sizes, result in decreasing MOS transistor sizes as well as the gate insulation or gate oxide becoming thinner. A thinner gate oxide or insulator in a MOS transistor results in exponential increases in stray current, such as leakage current, and forces opposing transistor switching, such as parasitic capacitances of the MOS device. Producing an integrated circuit (IC) has become increasingly difficult and unpredictable. Instead of producing more integrated circuit devices, these difficulties have resulted in fewer of the IC devices that meet performance or functions required.
Process-induced damage is also becoming a very serious concern for semiconductor device manufacturers. Such damage accounts for device degradations and lower yields. One type of process-induced damage is charge-induced damage. Charge-induced damage can occur during plasma etch and plasma-enhanced deposition processes often referred to as plasma charging damage, ash, and ion implantation. Charge-induced damage is becoming particularly serious due to the scaling down of gate oxide thicknesses and channel length with succeeding technologies, increasing levels of metallization, and the advent of high-density plasma sources for etching and deposition.
After assembling the thousands of unconnected cells for creating the IC, the interconnection of the cells can be achieved by a metallization process. Metallization includes the creation of a metal layer for interconnecting between the cells. A metal layer is made out of a conductive material such as metal according to a pattern specified to implement the particular IC function. In automated IC design, the metal layer pattern is created by routing that implements the specified IC function. The metal layer is processed according to the routed pattern. In the production of CMOS devices, plasma-etching techniques are used to produce the pattern on the metal layer. Metal layers are individually created and then connections are made between them as needed. This allows interconnections defined by pattern of the various metal layers to carry signals to and from cells in similar or different levels.
Interconnects in one metal layer may be connected to several gate inputs of MOS transistors before connections between the metal layer and other metal layers can be completed. Until the connections are completed, such gates remain open circuited and the interconnects that are attached to them behave as antennas. The antenna behaving interconnects receive static charge from the surrounding environment such as when a next higher metal layer is plasma-etched. Charges that accumulate in a gate capacitor can cause a gate-to-source voltage to exceed a breakdown voltage. An accumulation of charges on an open-circuited gate may result in a large enough charge to punch through the dielectric gate oxide. Since a gate oxide is extremely thin, it may easily be damaged by the excessive voltage. This effect is magnified as the length of interconnects increases.
As the density of MOS devices in IC increases, the structure of MOS devices gets smaller and, in turn, their respective gate oxide layers become even thinner. Moreover, to achieve higher performance and reduce power consumption, MOS devices, particularly CMOS devices, have been operating under lower supply voltage conditions and with smaller gate sizes. Hence, the accumulation of charges due to the antenna behavior of the interconnections becomes more critical. To prevent the accumulation of static charge in the gate capacitor of MOS devices, gate protection is usually included at the gate input of the MOS devices. The protection mechanism invariably makes use of clamping or antenna diodes often collectively referred to as antenna diodes. The function of the gate input protection is to limit the gate input voltage and prevent breakdown of the gate.
With respect to charge-induced damage, the charge collected in the antenna stresses the oxide of a device. More specifically, in a MOS device, the charge collected on the antenna stresses the gate oxide of the MOS device, thereby inducing stress-related degradation of the MOS device. This stress-related degradation may include shortening the lifetime of the device, increasing the gate leakage of the device, shifting the threshold voltage of the device, or rendering the device inoperable.
Thus, a need still remains for an integrated circuit system to improve integrated circuit modeling, performance, and size. In view of the ever-increasing commercial competitive pressures, coupled with the technical imperatives of improved die-to-die variation and improved production efficiency, it is critical that answers be found for these problems. Competitive pressures also demand lower costs alongside improved efficiencies and performance.
Solutions to these problems have been sought but prior developments have eluded those skilled in the art.